This invention relates generally to semiconductor memory structures, and more particularly, to very large memory arrays, which have a relatively high probability of containing defective memory cells. A semiconductor integrated-circuit memory takes the form of a two-dimensional array of memory cells fabricated together on a single semiconductor chip. Each memory cell typically stores one binary digit or bit of information, and the array is usually designed to store N "words" or information, each word being the same number of bits long. A common data word length is eight bits, which is referred to as a "byte." For convenience in handling binary cell addresses, the number of words in a memory array is usually a power of two, such as 1,024, 2,048, 4,096, and so forth. Each 1,024 words or bytes of memory is referred to as "1k" of memory. For example a "2 k" memory contains 2,048 words.
As the area of a semiconductor chip increases, so does the probability that there will be manufacturing defects within the chip. The manufacturing "yield" is the percentage of defect-free chips obtained in a production run. The probability of the occurrence of manufacturing defects in a unit surface chip area is approximately constant for a particular fabrication process. Therefore, larger chips will have more defects and a lower yield of defectfree circuits. Although the area of a specific circuit can be decreased by further reducing the scale of integration, i.e. by reducing the size of the circuit features and their spacing, this will ultimately result in an increase in the number of defects and a reduction in the yield.
An alternative to reducing the size of a circuit is to increase the effective production yield by rendering the resulting circuits more tolerant to defects, so that defective circuits can be repaired rather than discarded. Basically, this approach involves designing the circuit to include redundant or spare components, which can be logically connected into the circuit to replace components that have been found defective.
If there were an effective technique to render large circuits repairable in this manner, the maximum size of circuits could be greatly increased. In the past, integrated-circuit chips have been fabricated in multiple numbers on a much larger semiconductor wafer. At the end of the fabrication process, the wafer is "diced" into multiple circuit chips. If there were an effective technique for improving the effective yield of much larger chips, circuit size could be more easily increased to encompass an entire wafer. Prior to this invention, such wafer-scale integration has been limited by the approaches used to build redundancy into circuits such as large-scale memories.
Memory circuits are usually organized into arrays of rows and columns of one-bit cells. The usual approach for improving yield in large memory circuits is to include redundant storage cells that can be switched in on a row or column basis. There are a number of drawbacks to this approach. First, the spare rows or columns are good only for a low number of defects in particular configurations. Second, a related problem is that there is almost always a high proportion of unused good memory cells on the chip, even when the replacement capacity of the memory is exhausted. Another problem is that the replacement assignments are permanent. After testing and row or column replacement, if necessary, the circuit is packaged, and subsequently detected defects cannot be corrected.
Another source of circuit defects is radiation damage. This is highly significant for applications of circuitry to be used in a space environment where memory cells are there subject to damage by cosmic radiation. If only a single memory cell were to be damaged by cosmic radiation, the defect could be overcome by the use of an appropriate error detection and correction technique. A single-bit error in a relatively large data word can be detected and corrected without the need for reconfiguring the circuitry. However, there is a high probability that a cosmic radiation "strike" on a memory array would disable not just one cell, but several physically adjacent cells as well. If these damaged cells are all in the same data word, recovery by error detection and correction methods would not be possible. Accordingly, the ideal technique for reconfiguring a memory circuit should be one that minimizes the effects of radiation damage, and permits reconfiguration at any time after manufacture of the circuit. The present invention is directed to a memory system that provides a solution to the foregoing problems.